Sr Engineer (Formal Verification)
Arrow Electronics

San Jose, California

Posted in Electronics

This job has expired.

Job Info


Sr Engineer (Formal Verification)

Job Description:

* 6 to 10 years exp range.
* Minimum 2 years of experience in System Verilog HVL SVA Assertions.
* Must have executed at-least 2 SoC/IP Formal Verification signoff projects
* Must have used Synopsys VC Formal, Cadence Jasper or Questa Formal Tools comprehensively
* Hands on experience of developing Formal SV assertion/checkers, coverage register, regressions.
- Functional Checks/Assertions based Property coding to verify RTL Structures
- Data Path, Security, Register, Functional Safety and X Prorogation Verification
- Connectivity Checks on IP/SoC connections
- Fault Analysis using Formal Testbench Analyzer
- Formal Coverage and Regressions
* Support/Mentor new team in learning Formal Verification techniques and tools usage
* Assure compatibility of resources, tools, platform
* Work with customers through acceptance of deliverables.
* Ensure customer satisfaction.
* This job involves good written and verbal skills.
* Highly motivated technical person with business development is required. Team player

BSEE/MSEE/BSCompE/MSCompE with 6 to 10 years of industry experience

Annual Hiring Range/Hourly Rate:

$126,000.00 - $154,000.00

Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.


US-CA-San Jose, California (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)

This job has expired.

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